The transfer of digital data between digital circuits is well known. Depending on the type of digital circuit, the transfer of the digital data may be done in a synchronous manner or an asynchronous manner. For example, if the digital circuits are logic circuits (i.e., circuits that consist of a plurality of logic gates such as NOR gates, AND gates, etc.) the digital data can be transferred asynchronously. In other words, as soon as the logic circuits have performed their function upon the digital data, they may present the manipulated digital data to the next logic circuit for its processing. It is also well known that logic circuits may transfer the digital data in a synchronous manner by including latches at the input and output of the logic circuits. With these synchronous logic circuits, when the input latch is activated, the digital data is received by the logic circuit which then processes the digital data. The manipulated digital data is not provided as an output until the output latch is triggered, or clocked. At this time, the manipulated digital data is presented to the input of the next logic circuit.
When the digital data is being transferred between a processing device, such as a microprocessor, digital signal processor (DSP), processing circuit, or the like, and a memory device, the data transfer is done in a synchronous manner. To synchronize the processing device and the memory device, both are coupled to the same clock, thereby assuring that the data is transferred in a controlled and reliable manner. While operating the memory device and the processing device from the same clock works well when both device have approximately the same operating rate (i.e., the speed at which the device can assimilate data), it is inefficient to operate the devices from the same clock when they have substantially different operating rates. The inefficiency arises in that it is desirable to have each device operating at, or near, its maximum operating rate, such that it can process as much data as possible in a given time period. With the substantial differences in the operating rates, the faster device usually has to wait for the slower device to assimilate its data before performing its function or the system containing the devices would need to operate at a rate equal to the slowest of the devices.
To transfer data efficiently between low speed devices (operating rates less than 100 KHz) and high speed devices (operating rates above 10 MHz), the data is buffered such that each device can read and/or write to and from the buffer at its maximum speed. A display refresh module in a video graphics circuit communicating data with video memory is an example of a different speed device communicating with another device using buffering. In this example, however, the communicating of the data is a continuous read of the data, not a discontinuous read/write function.
In the video graphics processing technology, video graphics processing modules (such as graphical user interface modules, desktop display modules, video scaling module, video capture module, etc.) have substantially the same operating rate as the video memory. Typically, these modules and the video memory are coupled to a master clock of 50-83 MHz. As such, the transfer of digital data between the modules and the video memory is done in a discontinuous data burst manner at a common operating rate. A new development, however, is occurring within the video graphics art as the operating rate of the video memory is surpassing the operating rate of the video modules. For example, video memory may soon have an operating rate (i.e., be able to read and/or write data) of 100-150 MHz.
This increase in video memory operating rate presents a new and interesting problem to the video graphics art, in that, the operating rate of the video modules will soon be much slower than the video memory. As is well understood in the art, video modules, such as the graphical user interface, have a limited operating rate due to the complex digital logic they employ. Even using the latest digital logic integrated circuit techniques, the logic circuits can only switch so fast, thus limiting the speed of the graphical user interface to about 80 MHz. If a video graphics circuit includes a graphical user interface that operates at about 80 MHz and video memory that operates at 150 MHz, it would be inefficient to slow the video memory down just to accommodate the graphical user interface.
One potential solution to overcome the above mentioned inefficiency is to redesign the graphical user interface module into many more smaller logical circuits which are less complex and can therefore process the data faster. While this will provide the needed increase in speed, it requires the graphical user interface to include considerably more latching circuits to clock the data into and out of the smaller digital logic sections. Such an increase in components consequently increases the size of the circuit and its power consumption; two issues IC designers continually fight to reduce. As such, redesigning the graphical user interface, or any other video module, in this manner is not a desirable solution due to the increase in size and power consumption.
Another issue is that the speed of various video memory technologies differs greatly. As one can appreciate, the cost of video memory is largely dependent upon its speed. If a system were built that included video memory that operated at 50 MHz, it would be undesirable to slow down the rest of the graphical user interface which is capable of operating at 80 MHz.
Therefore, a need exists for a method and apparatus that allows video graphics modules and video memory to operate at optimum operating rates without an increase in power consumption or an increase in the size of the modules.